Digital Signal Processing with FPGA
PDF Course Catalog Deutsche Version: DSF
Version: 3 | Last Change: 13.09.2019 11:21 | Draft: 0 | Status: vom verantwortlichen Dozent freigegeben
Long name | Digital Signal Processing with FPGA |
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Approving CModule | DSF_BaET, DSF_BaTIN |
Responsible |
Prof. Dr. Jens Onno Krah
Professor Fakultät IME |
Valid from | summer semester 2023 |
Level | Bachelor |
Semester in the year | summer semester |
Duration | Semester |
Hours in self-study | 60 |
ECTS | 5 |
Professors |
Prof. Dr. Jens Onno Krah
Professor Fakultät IME |
Requirements | TI1, DSS, SuS |
Language | German |
Separate final exam | Yes |
Elektronische Bedienhandbücher und Tutorials für Programmiersystem des FPGA-Herstellers |
Skript (pdf) |
Details | Written module examination - similar to the exercises |
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Minimum standard | - |
Exam Type | EN Klausur |
Goal type | Description |
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Skills | Basics of digital signal processing, Time-discrete systems Analog-to-digital conversion and sample-and-hold Sigma delta modulation, quantization noise Practical application of z-transformation Design of digital filters (IIR and FIR) fixed-point arithmetic Implementation in a DSP environment ("C" + Assembler) Implementation in an FPGA environment ("VHDL") FPGA development system Quartus II Introduction of the FPGA series Max 10 from Altera / Intel Eclipse / Nios II development environment |
Type | Attendance (h/Wk.) |
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Lecture | 2 |
Exercises (whole course) | 2 |
Exercises (shared course) | 0 |
Tutorial (voluntary) | 0 |
none |
Accompanying material |
Lecture script (pdf) Exercise collection (pdf) |
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Separate exam | No |
Goal type | Description |
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Skills | Practical application of z-transformation Implementation in an FPGA environment ("VHDL") FPGA development system Quartus II Introduction of Altera's Max 10 FPGA Series / Intel Nios II development environment |
Type | Attendance (h/Wk.) |
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Practical training | 1 |
Tutorial (voluntary) | 0 |
none |
Accompanying material | Internship Instructions (pdf) |
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Separate exam | No |
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