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---+!! Course %FORMFIELD{"Bezeichnung"}%


%TOC{depth="3"}%
%STARTSECTION{"no_toc"}%
---
*Responsible:* Prof.Dr.Thieling

---++ Course
---+++ Meets requirements of following modules(MID)
   * in active programs
      * [[BaET2012_DT]]
      * [[BaTIN2012_DT]]

---+++ Course Organization
<sticky>
  <table border="0">
    <tr valign="top">
      <td>
        <table border="1" cellpadding="2" cellspacing="0">
          <th colspan="2">Version</th>
          <tr>
            <td>created</td>
            <td>2013-07-24</td>
          </tr>
          <tr>
            <td>VID</td>
            <td>1</td>
          </tr>
          <tr>
            <td>valid from</td>
            <td>WS 2012/13</td>
          </tr>
          <tr>
            <td>valid to</td>
            <td/>
          </tr>
        </table>
      </td>
      <td>         </td>
      <td>
        <table border="1" cellpadding="2" cellspacing="0">
          <th colspan="2">Course identifiers</th>
          <tr>
            <td>Long name</td>
            <td>%FORMFIELD{"Bezeichnung"}%</td>
          </tr>
          <tr>
            <td>CID</td>
            <td>F07_DT</td>
          </tr>
          <tr>
            <td>CEID (exam identifier)</td>
            <td/>
          </tr>
        </table>
      </td>
    </tr>
  </table>
</sticky><sticky>
  <table border="0">
    <tr valign="top">
      <td>
        <table border="1" cellpadding="2" cellspacing="0">
          <th colspan="2">Contact hours per week (SWS)</th>
          <tr>
            <td>Lecture</td>
            <td>%FORMFIELD{"VorlesungSWS"}%</td>
          </tr>
          <tr>
            <td>Exercise (unsplit)</td>
            <td>%FORMFIELD{"UebungGanzSWS"}%</td>
          </tr>
          <tr>
            <td>Exercise (split)</td>
            <td>%FORMFIELD{"UebungHalbSWS"}%</td>
          </tr>
          <tr>
            <td>Lab</td>
            <td>%FORMFIELD{"PraktikumSWS"}%</td>
          </tr>
          <tr>
            <td>Project</td>
            <td>%FORMFIELD{"ProjektSWS"}%</td>
          </tr>
          <tr>
            <td>Seminar</td>
            <td>%FORMFIELD{"SeminarSWS"}%</td>
          </tr>
          <tr>
            <td>Tutorial(voluntary)</td>
            <td>%FORMFIELD{"TutoriumSWS"}%</td>
          </tr>
        </table>
      </td>
      <td>    </td>
      <td>
        <table border="1" cellpadding="2" cellspacing="0">
          <th colspan="2">Total contact hours</th>
          <tr>
            <td>Lecture</td>
            <td>%FORMFIELD{"VorlesungPZ"}%</td>
          </tr>
          <tr>
            <td>Exercise (unsplit)</td>
            <td>%FORMFIELD{"UebungGanzPZ"}%</td>
          </tr>
          <tr>
            <td>Exercise (split)</td>
            <td>%FORMFIELD{"UebungHalbPZ"}%</td>
          </tr>
          <tr>
            <td>Lab</td>
            <td>%FORMFIELD{"PraktikumPZ"}%</td>
          </tr>
          <tr>
            <td>Project</td>
            <td>%FORMFIELD{"ProjektPZ"}%</td>
          </tr>
          <tr>
            <td>Seminar</td>
            <td>%FORMFIELD{"SeminarPZ"}%</td>
          </tr>
          <tr>
            <td>Tutorial (voluntary)</td>
            <td>%FORMFIELD{"TutoriumPZ"}%</td>
          </tr>
        </table>
      </td>
      <td>    </td>
      <td>
        <table border="1" cellpadding="2" cellspacing="0">
          <th colspan="2">Max. capacity</th>
          <tr>
            <td>Exercise (unsplit)</td>
            <td>%FORMFIELD{"UebungGanzTeilnehmer"}%</td>
          </tr>
          <tr>
            <td>Exercise (split)</td>
            <td>%FORMFIELD{"UebungHalbTeilnehmer"}%</td>
          </tr>
          <tr>
            <td>Lab</td>
            <td>%FORMFIELD{"PraktikumTeilnehmer"}%</td>
          </tr>
          <tr>
            <td>Project</td>
            <td>%FORMFIELD{"ProjektTeilnehmer"}%</td>
          </tr>
          <tr>
            <td>Seminar</td>
            <td>%FORMFIELD{"SeminarTeilnehmer"}%</td>
          </tr>
        </table>
      </td>
    </tr>
  </table>
</sticky>

*Total effort (hours):* %FORMFIELD{"Gesamtaufwand"}%

---++++ Instruction language
   * Deutsch

---++++ Study Level
   * %FORMFIELD{"Niveau"}%
---++++ Prerequisites
   * none

---++++ Textbooks, Recommended Reading
   * Urbanski K., Woitowikz R.: Digitaltechnik, 4. Auflage Springer 2004
   * Beuth K.: Elektronik Bd. 4 Digitaltechnik, Vogel Verlag 2001
   * Lipp H.M.: Grundlagen der Digitaltechnik, 4. Auflage Oldenbourg 2002

---++++ Instructors
   * Prof. Dr. Thieling
   * Prof. Dr. Hartung



---++++ Supporting Scientific Staff
   * Dipl.-Ing. Peter Pohlig

---++++ Transcipt Entry
Digital Systems

---+++ Assessment
<sticky>
  <table border="1" cellpadding="2" cellspacing="0">
    <th colspan="2">Type</th>
    <tr>
      <td>wE</td>
      <td>normal case (except on small numbers of assessments: oE</td>
    </tr>
  </table>
</sticky>

<sticky>
  <table border="1" cellpadding="2" cellspacing="0">
    <th colspan="2">Total effort [hours]</th>
    <tr>
      <td>wE</td>
      <td>10</td>
    </tr>
  </table>
</sticky>

*Frequency:* 3/Jahr

-----
---++ Course components

%STARTSECTION{"Vorlesung / Übung"}%
---+++ <u>Lecture/Exercise</u>

---++++ Objectives 
---+++++ Contents
   * boolean algebra
      * basic functions
      * axioms and laws
      * disjunctive normal form, minterms
      * conjunctive normal form, maxterms
      * systematic simplification
   * boolean network
      * logic gates, tri-state buffer
      * description forms
         * boolean equation
         * table
         * KV diagram
         * schematic
      * transformations between the forms of description
      * analysis
      * synthesis (including transfer from text to problem solution)
      * don't-care conditions
      * typical networks
         * decoder
         * multiplexer
         * demultiplexer
         * adder
      * hazards
         * static hazard
         * function hazard
         * dynamic hazard
         * avoid hazards
   * codes
      * weighted codes
         * dual
         * hexadecimal
         * octal
         * change of basis
      * BCD codes and their applications
      * gray codes and their applications
      * properties
         * redundancy
         * hamming distance
         * cyclicness
      * parity ans block codes
      * number representation in computer systems
         * two's complement
         * fixed point representation
         * floating point representation
         * ASCII-code
   * feedback networks
      * flip-flops and latches
         * RS
         * D
         * JK
         * asynchronous control
         * clock state control
         * edge triggered
      * registers
         * parallel read-write register
         * shift register
         * parallel-serial conversion
         * seria-parallell conversion
      * practice-oriented specifications
         * setup time
         * hold time
         * minimum puls width
   * synchronous counters
      * the basic idea
      * construction using D flip-flops
         * analysis
         * synthesis
      * specification using VHDL
         * refer VHDL
   * finite state machines
      * description of state machines using state transition diagrams (Moore and Mealy)
      * design of state machines as a problem-solving
      * implementation using D-flops
      * Implementation using VHDL
   * state transition diagrams
      * modeling according to Moore
      * modeling according to Mealy
      * conversion between Moore and Mealy
      * advantages and disadvantages of Mealy and Moore
      * characteristics (determinism, completeness) 
   * VHDL
      * specification of boolean networks
         * structure of a VHDL program (entity, port, architecture, signals, in, out)
         * signals (type stdlogic:  1, 0, Tri-State, Don't-Care) 
         * signal assignment (direct implementation of boolean functions)
         * conditional signal assignment (direct conversion of tables)
         * vectors of signals
         * integer data type and conversion from/to signal vectors
         * design entry VHDL
      * specification of counters and finite state machines
         * processes and sequential instructions (process, variable, if, case, event, type)
         * implementation of regular counter in VHDL
         * implementation of finite state machines in VHDL
   * programmable logic devices
      * structure
         * the basic idea
         * technology
         * CPLD versus FPGA 
      * design tool
         * scematic design entry
            * basic library (gates, in, ou, buffer, mux, decoder, flip-flops) 
            * buses
            * hierarchical schematics
         * VHDL design entry
            * detail refer VHL
         * synthesis
         * simulation
            * without propagation delay
            * with propagation delay
   *  structure and mode of operation of a simple computer
      * structure of a Von Neumann computer (registers, arithmetic logic unit, control unit, memory, buses)
      * mode of operation (program execution based on register transfers)
      * concretization of mode of operation (a minimal simulated Von Neumann computer)
      * programming the minimal computer in assembler (simple loops, different addressing modes)

---+++++ Acquired Skills
   * specifying system behavior (derived from text documents)
   * development of problem solutions that can be implemented with boolean networks
   * interpretation and convertion of codes
   * development of problem solutions that can be implemented with synchronous counters
   * development of problem solutions that can be implemented with finite state machines
   * explain the operation of a Von Neumann computer


---++++ Additional Component Assessment 
   * none

%ENDSECTION{"Vorlesung / Übung"}%



%STARTSECTION{"Praktikum"}%
---+++ <u>Lab</u>

---++++ Objectives 
---+++++ Acquired Skills
   * development od digital systems
   * explain the system behavior of a Von Neumann computer
   * implement subsystems of a Von Neumann computer
   * implementation of  C-code sequences using assembler

---+++++ Operational Competences
   * manage complex tasks as a small team
   * develop problem solutions


---++++ Additional Component Assessment 
   * none

%ENDSECTION{"Praktikum"}%




%ENDSECTION{"no_toc"}%
Topic-Revision: r5 - 11 Jan 2016, GeneratedContent
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