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<!-- * Set USERSTYLEURL = %PUBURLPATH%/%WEB%/DokumentFormat/fonts.css --> ---+!! Course %FORMFIELD{"Bezeichnung"}% %TOC{depth="3"}% %STARTSECTION{"no_toc"}% --- *Responsible:* Prof. Dr. Hartung ---++ Course ---+++ Meets requirements of following modules(MID) * in active programs * [[BaET2012_GTI]] ---+++ Course Organization <sticky> <table border="0"> <tr valign="top"> <td> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Version</th> <tr> <td>created</td> <td>2013-07-14</td> </tr> <tr> <td>VID</td> <td>1</td> </tr> <tr> <td>valid from</td> <td>WS 2012/13</td> </tr> <tr> <td>valid to</td> <td/> </tr> </table> </td> <td> </td> <td> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Course identifiers</th> <tr> <td>Long name</td> <td>%FORMFIELD{"Bezeichnung"}%</td> </tr> <tr> <td>CID</td> <td>F07_GTI</td> </tr> <tr> <td>CEID (exam identifier)</td> <td/> </tr> </table> </td> </tr> </table> </sticky><sticky> <table border="0"> <tr valign="top"> <td> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Contact hours per week (SWS)</th> <tr> <td>Lecture</td> <td>%FORMFIELD{"VorlesungSWS"}%</td> </tr> <tr> <td>Exercise (unsplit)</td> <td>%FORMFIELD{"UebungGanzSWS"}%</td> </tr> <tr> <td>Exercise (split)</td> <td>%FORMFIELD{"UebungHalbSWS"}%</td> </tr> <tr> <td>Lab</td> <td>%FORMFIELD{"PraktikumSWS"}%</td> </tr> <tr> <td>Project</td> <td>%FORMFIELD{"ProjektSWS"}%</td> </tr> <tr> <td>Seminar</td> <td>%FORMFIELD{"SeminarSWS"}%</td> </tr> <tr> <td>Tutorial(voluntary)</td> <td>%FORMFIELD{"TutoriumSWS"}%</td> </tr> </table> </td> <td> </td> <td> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Total contact hours</th> <tr> <td>Lecture</td> <td>%FORMFIELD{"VorlesungPZ"}%</td> </tr> <tr> <td>Exercise (unsplit)</td> <td>%FORMFIELD{"UebungGanzPZ"}%</td> </tr> <tr> <td>Exercise (split)</td> <td>%FORMFIELD{"UebungHalbPZ"}%</td> </tr> <tr> <td>Lab</td> <td>%FORMFIELD{"PraktikumPZ"}%</td> </tr> <tr> <td>Project</td> <td>%FORMFIELD{"ProjektPZ"}%</td> </tr> <tr> <td>Seminar</td> <td>%FORMFIELD{"SeminarPZ"}%</td> </tr> <tr> <td>Tutorial (voluntary)</td> <td>%FORMFIELD{"TutoriumPZ"}%</td> </tr> </table> </td> <td> </td> <td> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Max. capacity</th> <tr> <td>Exercise (unsplit)</td> <td>%FORMFIELD{"UebungGanzTeilnehmer"}%</td> </tr> <tr> <td>Exercise (split)</td> <td>%FORMFIELD{"UebungHalbTeilnehmer"}%</td> </tr> <tr> <td>Lab</td> <td>%FORMFIELD{"PraktikumTeilnehmer"}%</td> </tr> <tr> <td>Project</td> <td>%FORMFIELD{"ProjektTeilnehmer"}%</td> </tr> <tr> <td>Seminar</td> <td>%FORMFIELD{"SeminarTeilnehmer"}%</td> </tr> </table> </td> </tr> </table> </sticky> *Total effort (hours):* %FORMFIELD{"Gesamtaufwand"}% ---++++ Instruction language * Deutsch ---++++ Study Level * %FORMFIELD{"Niveau"}% ---++++ Prerequisites * keine ---++++ Textbooks, Recommended Reading * Vogt, C: C für Java-Programmierer * Tanenbaum, Goodman: Computerarchitektur, Pearson Studium (Prentice Hall) ---++++ Instructors * Prof.Dr.Hartung * Prof.Dr.Thieling * Prof. Dr. Kreiser ---++++ Supporting Scientific Staff * Dipl.-Ing. Norbert Kellersohn * MSc. Hanna Sidnenka ---++++ Transcipt Entry Basics of Computer Engineering ---+++ Assessment <sticky> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Type</th> <tr> <td>oE</td> <td/> </tr> </table> </sticky> <sticky> <table border="1" cellpadding="2" cellspacing="0"> <th colspan="2">Total effort [hours]</th> <tr> <td>sK</td> <td>10</td> </tr> </table> </sticky> *Frequency:* 3/year ----- ---++ Course components %STARTSECTION{"Vorlesung / Übung"}% ---+++ <u>Lecture/Exercise</u> ---++++ Objectives ---+++++ Contents * Basic knowledge in automata theory * Boolean Algebra (B.A.) * Use B.A. to describe simple logical systems * computation laws of B.A. * normal forms * network of B,A, functions * Codes used in digital systems and computers * number representation (integer, float) * character coding * ASCII * binary codes for measurement data * error handling * adding parity * Finite Discrete Automata (FSA) * Mealy * Moore * Transformation model to code * code generation (C) * code generation (VHDL) * Basic knowledge in digital technology * description * schematic * hardware description language (VHDL) * logical units (gates) * standard gates * elementary gates AND, OR, NOT, XOR * decoder, multiplexer * configurable gates * basics of C programming for controllers * constants, variables, data representation * expressions * bit operations * statements, control structures * references, pointer, pointer arithmetics * functions * f. with reference parameters * variables in functions * auto, static, volatile, register * standard libraries * stdio * string * structuring of data (struct, union) * preprocessor statements * multi file sources with library access * I/O programming with C * hardware of I/O ports * access to I/O * memory mapped I/O * separate port area * direct I/O access via pointer * I/O driver: functional model and access * bit access and manipulation with C * software development for Microcontroller * Compiler * Linker * (Target-)Debugger * Simulator * programming of measurement and control systems * transformation of Moore and Mealy FSA into C programs * example: development of an application-oriented I/O library * structure and function of a embedded computer system (microcontroller) * architecture (processor with control and computation unit), parallel, serial I/O, timer, ADC * function of processor in a register transfer model * exceptions and interrupts * interrupt sources * interrupt management * I/O processing via interrupt in an example ---+++++ Acquired Skills * Understanding technical specifiations (data sheets) * Using description techniques * transformation of boolean functions * FSA description * digital system construction * using specification tools * writing VHDL models * using synthesis tools for FPGA configuration * test with test vectors * measurement and control with mini/microcontroller * use of driver libraries inclusive interrupt * programming the system with C ---++++ Additional Component Assessment * keiner %ENDSECTION{"Vorlesung / Übung"}% %STARTSECTION{"Praktikum"}% ---+++ <u>Lab</u> ---++++ Objectives ---+++++ Acquired Skills * digital system construction * specification using a electronic design tool (e.g. Altera Quartus II) * implementation * configuration of FPGA * test FPGA in lab * mini/microcontroller system construction * interpretation of student-adapted technical description * using a programming environment with driver functions * implementation of program ---+++++ Operational Competences * handle complex tasks in a small team * Specification, implementation and test of an digital example system * with FPGA * with mini/microcontroller * understanding a textual description of medium size with different aspects * system behavior * system architecture * understanding system levels * understanding interfaces ---++++ Additional Component Assessment * keiner %ENDSECTION{"Praktikum"}% %ENDSECTION{"no_toc"}%
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Topic-Revision: r3 - 11 Jan 2016,
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